In recent years, it is getting more difficult to detect failures in LSIs because the scales and complexities of LSIs are increased. As an example of methods for detecting the failures, there is a semiconductor inspection method which detects stuck-at failures from circuit data of a logical circuit.
Hereinafter, a description is given of a prior art semiconductor inspection method for detecting stuck-at failures in a logical circuit which comprises a three-input AND gate and a two-input AND gate.
FIG. 2 is a diagram illustrating the logical circuit comprising the three-input AND gate and two-input AND gate. FIG. 3 is a diagram illustrating a layout pattern of the logical circuit shown in FIG. 2. FIGS. 6(a)-6(c) are truth tables showing input logical values and output logical values corresponding thereto, which are used in the prior art semiconductor inspection method.
The logical circuit 200 shown in FIG. 2 includes a three-input AND gate 210 and a two-input AND gate 211. Input to the three-input AND gate 210 is performed through input terminals 201, 202 and 203. Input to the two-input AND gate 211 is performed through input terminals 203 and 204. Outputs from the three-input AND gate 210 and two-input AND gate 211 are performed through output terminals 206 and 207, respectively.
Next, the prior art semiconductor inspection method is described in detail.
Initially, in the three-input AND gate 210, when “1”s are input to the input terminals 201-203 as inputs A-C, respectively, as shown in logical column (a) of the truth table in FIG. 6(a), and an output E of the output terminal 206 is monitored, “0” stuck-at failures in the terminals 201-203 and 206 are detected. In addition, when “0” is input to the input terminal 201 as the input A and “1”s are input to the input terminals 202 and 203 as the inputs B and C, respectively, as shown in logical column (b) of the truth table, and the output E of the output terminal 206 is monitored, “1” stuck-at failures in the terminals 201 and 206 are detected. Similarly, when “0” is input to the input terminal 202 as the input B and “1”s are input to the input terminals 201 and 203 as the inputs A and C, respectively, as shown in logical column (c) of the truth table, and the output E of the output terminal 206 is monitored, or when “0” is input to the input terminal 203 as the input C and “1”s are input to the input terminals 201 and 202 as the inputs A and B, respectively, as shown in logical column (d) of the truth table, and the output E of the output terminal 206 is monitored, “1” stuck-at failures in the input terminals 202 and 203 are detected. Thus, when the combinations of the input logical values shown in the truth table of FIG. 6(a) are input to the terminals, the stuck-at failures in the terminals 201-203 and 206 are detected. Further, the combinations of the input logical values shown in the truth table in FIG. 6(a) have good detection efficiency and failures can be detected with fewer combinations. Accordingly, these combinations are conventionally generally used.
Similarly, also in the two-input AND gate 211, when input logical values as shown in logical column (e) of the truth table in FIG. 6(b) are input to the input terminals 203 and 204 and an output F of the output terminal 207 is monitored, the “0” stuck-at failures in the terminals 203, 204 and 207 are detected. In addition, when input logical values as shown in logical columns (f) and (g) of the truth table in FIG. 6(b) are input to the input terminals 203 and 204 and the respective outputs F of the output terminal 207 are monitored, the “1” stuck-at failures in the terminals 203, 204 and 207 are detected. Therefore, in the logical circuit 200 shown in FIG. 2, when input logical values as shown in logical columns (h)-(k) of the truth table in FIG. 6(c), which is obtained by combining the logical columns (a)-(d) of the truth table in FIG. 6(a) as necessary combinations for detecting the stuck-at failures in the three-input AND gate 210 and the logical columns (e)-(g) of the truth table in FIG. 6(b) as necessary combinations for detecting the stuck-at failures in the two-input AND gate 211, are input to the input terminals 201-204 as the inputs A-D, and the outputs E and F of the output terminals 206 and 207 are monitored, the “0” stuck-at failure and “1” stuck-at failure in the terminals 201-204, 206 and 207 are detected.
Here, in a case where the logical circuit 200 shown in FIG. 2 has a layout pattern as shown in FIG. 3 on a semiconductor, when the input logical values shown in logical columns (h)-(k) of the truth table in FIG. 6(c) given by the prior art semiconductor inspection method for detecting the stuck-at failure are input to the input terminals 201-204, the “0” stuck-at failure and “1” stuck-at failure in the terminals 201-204, 206 and 207 can be detected. However, in this case, since the logical values output from the output terminals 206 and 207 are the same, even when the output terminals 206 and 207 are short-circuited, the short circuit of the terminals cannot be detected. As described above, in the prior art semiconductor inspection method, there are some cases where short circuit failures cannot be detected and failures in LSIs or the like cannot be detected.